Seminar

One of the primary approaches to hardware description in processor and system-on-chip design is register-transfer level (RTL) description using the Verilog and SystemVerilog languages. In large projects, RTL descriptions reach hundreds of thousands to millions of lines. Defects introduced into an RTL description are often found only at late design stages, when fixing them is expensive. Static analysis can detect such defects before simulation and logic synthesis. However, industrial analyzers are closed to extension, and open-source tools neither fully support SystemVerilog nor analyze finite state machines. The talk presents a static analysis method for digital hardware descriptions based on a multi-level intermediate representation built on top of the elaborated design model. A set of 118 rules is formulated, and each rule is mapped to an analysis technique sufficient to check it: abstract syntax tree traversal, path analysis with interval constraints, data-flow analysis with signal value range tracking, and others. A domain-specific language for matching syntax tree nodes is proposed for developing rule detectors. A method for extracting finite state machines from the gate-level network is developed that does not depend on the coding style. The method detects dead transitions, unreachable states, deadlocks and livelocks, the latter two defined through terminal strongly connected components of the state graph. A unified information model links the hardware description with Liberty cell libraries, UPF power intent and SDF delay descriptions. Based on this model, a static check of isolation and level-shifter strategies is developed. The methods are implemented in the SVAN static analysis system. Evaluation on ten open-source designs totaling over 1.8 million lines shows a rule detector precision of 96.3 % and a state machine analysis precision of 95.5 %. Developers of the open-source designs confirmed 13 of the 24 reported violations. The talk also covers a comparison with the commercial tool SpyGlass and five open-source static tools.

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